october 2004 1/4 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rev. 4 stpc? vega x86 core pc compatible soc with ethernet and usb data brief pentium ? ii class processor core 64-bit sdram controller running at up to 100 mhz pci 2.1 compliant master/slave controller isa master / slave dual port usb host controller (ohci) 10/100 ethernet mac 1) integrated peripheral controller with suppport for external rtc ultra dma-66 ide controller power management unit 16-bit local bus interface i2c bus controller uart (1 rxtx) ieee 1149.1 jtag interface 8 general purpose io programmable clocks 0.18 micron technology 1.8 v core & 3.3 v i/os low power consumption device description the stpc vega integrates a fully static pentium ? ii ? class processor, fully compatible with industry standards, and combines it with a powerful chipset to provide a general purpose pc compati- ble subsystem on a single device. the device is packaged in a 388 ball grid array (pbga). 1- the usage of the internal mac 10/100 is very restricted. for more information see 10/100 ethernet controller description. 1 pbga388 s t p c v e g a p-ii? class core host i/f sdram i/f pci i/f pci uide isa i/f pci i/f isa bus lb i/f local bus ipc jtag pmu gpio usb 10/100 mac i 2 c isa bus block diagram
stpc? vega 2/4 x86 processor x86 pentium? ii class processor running in x2 mode -3 issue integer six-stage pipeline/clock -3 issue mmx?/clock -pipelined fpu bus clock with skew correction internal core clocks generated as multiples of bus clock with multiplic ation factors of x2, x2.5, x3, x3.5 sdram interface 64-bit data bus 100 mhz maximum sdram clock 8 mbyte to 256 mbyte memory size (only the upper 128mbyte cacheable) supports 16 mbit to 256 mbit memories support for -8 to -15 memory parts supports buffered and non-buffered dimms supports registered dimms programmable latency pci controller master/slave compatible with pci vers ion 2.1 specification integrated pci arbitration interface. up to three external masters can be directly connected master/slave bridge to usb, lan, uide & isa cycles support for burst read/write from pci master 0.20x, 0.25x, 0.33x and 0.5x host clock pci clock. automatically selected. isa master/slave generates the isa clock from either 14.318 mhz oscillator clock or pci clock supports programmable extra wait state for isa cycles supports i/o recovery time for back to back i/o cycles fast gate a20 and fast reset supports flash rom supports isa hidden refresh buffered dma and isa master cycles to reduce the bandwidth utilization of pci and system bus local bus multiplexed with isa interface 16-bit bus data path with word steering capability two cacheable banks of 32 mbyte flash devices (boot block shadowed from 000c0000h to 000fffffh) programmable timing with host clock granularity for flash accesses 32-bit flash burst support two-level hardware key protection for flash boot block protection up to eight io devices (four chipselects) supported with programmable start address & size io device timing (setup & recovery time) programmable integrated peripherals controller interrupt controller: 8259 compatible (two interrupt controllers) dma controller: 8237 co mpatible (two dma controllers) page register counter 0 and counter 1 gates are always on, counter 2 is controlled by writing to port b supports external rtc ultra dma-66 ide controller supports ide hard drives larger than 528 mbytes support for two connectors to allow up to four drives support for cd-rom and tape peripherals support for 11.1/16.6 mbytes/second, i/o channel ready pio data transfers supports up to 66 mbytes/second, udma data transfers ultra dma supports crc-16 error checking protocol (no correction supported) pio: 0 to 5, dma: 0 to 2, udma: 0 to 4 backward compatibility with ide (ata-1) 8 gpio individual pins programmable as either input or output interrupt generation with selectable masking 1
stpc? vega 3/4 10/100 ethernet controller the usage of vega internal mac is very restricted and tested only under linux operating system with the specific configuration 100mb/s half and full duplex . any other functional configuration is not guaranteed by stmicroelectronics. problem that maybe occur is a file transfer corruption , however the use of the internal mac for browsing applications or http session does not causes problem. compliant with ieee 802.3, 802.3u specification supports 10/100 mb/s data transfer rates ieee 802.3 compliant mii interface to talk to an external physical layer (phy) vlan support supports both full-duplex and half-duplex operations supports csma/cd protocol for half-duplex supports flow-control for full-duplex operation collision detection and auto retransmission on collisions in half-duplex mode management support using a variety of counters preamble generation and removal automatic 32-bit crc generation and checking optional insertion of pad/crc32 on transmit options for automatic pad stripping on the receive packets provides external and internal loop back capability on the mii interface contains a variety of flexible address filtering modes on the ethernet side: - one 48-bit perfect address - 64 hash-filtered multicast addresses - pass all multicast addresses - promiscuous mode - pass all incoming packets with a status report usb host controller open hci rev 1.1 compatible usb rev 1.1 compatible root hub with two down-stream ports with power switching control support of both low & high speed usb devices support of system management interupt (smi) uart one uart rxtx only programmable word length, stop bits and parity programmable baud rate generator interrupt generator loop-back mode scratch register two 16-byte fifos power management unit four power saving modes: on, doze, standby, suspend programmable system activity detector supports stpclk# i2c bus controller one i2c compliant master/slave bus controller slow and fast modes supported jtag function boundary scan chain function 1
stpc? vega 4/4 notes information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 1
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